Shift registers are core circuit units of integrated circuits that are used in products such as thin film transistor liquid crystal displays (TFT-LCDs). A shift register provides sequential pulse signals to scanning lines of a TFT-LCD, so as to control on and off states of TFTs connected to the scanning lines.
Referring to FIG. 6, one such shift register unit 100 includes a first clock inversion circuit 110, an inverter 120, and a second clock inversion circuit 130. All transistors in the first clock inversion circuit 110, the inverter 120, and the second clock inversion circuit 130 are PMOS (P-channel metal oxide semiconductor) transistors. The first clock inversion circuit 110 receives an output signal VS from a pre-stage shift register unit (not shown). The output signal VS functions as a start signal.
The first clock inversion circuit 110 includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a first output VO1, and a second output VO2. The inverter 120 includes a fifth transistor M5 and a sixth transistor M6. The inverter 120 outputs an output signal that serves as a shift register signal VO. The second clock inversion circuit 130 and the first clock inversion circuit 120 have similar structures. The second clock inversion circuit 130 includes a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, and a tenth transistor M10.
Referring to FIG. 7, a sequence waveform diagram of pulse signals of the shift register unit 100 is shown. During a period t1, the inverter 120 and the second clock inversion circuit 130 perform a latch operation. During the latch operation, the sixth transistor M6 is switched off such that the shift register signal VO of the inverter 120 keeps an original state of the previous stage. During a period t2, no latch operation is performed. The start signal VS is applied to the inverter 120, and the second clock inversion circuit 130 keep the same state as the start signal VS. Furthermore, the first transistor M1 is switched on because the start signal VS jumps to a low voltage, such that the fifth transistor M5 is switched off and the sixth transistor M6 is switched on. Thus, the inverter 120 outputs the shift register signal VO having a low level through the activated sixth transistor M6. During a period t3, the inverter 120 and the second clock inversion circuit 130 perform latch operation the inverter 120 maintains output of a low level shift register signal VO through the activated sixth transistor M6. During a period t4, no latch operation is performed. The inverter 120 stops output of the low-level shift register signal VO.
The shift register unit 100 outputs a low level shift register signal during period t2, and at the same time, the next-stage shift register unit (not shown) also outputs a low level shift register signal. Thus, adjacent shift register units (e.g., the shift register unit 100 and the next-stage shift register unit) may cause signal distortions between adjacent shift register units due to overlapping adjacent shift register signals. As a result, the shift register unit 100 is liable to be unstable. Accordingly, an LCD device employing the shift register unit 100 may have a distorted display quality because adjacent scanning lines corresponding to adjacent columns or rows of TFTs may be scanned simultaneously by the shift register pulse signals instead of being scanned sequentially. Furthermore, because the first voltage VDD is directly connected to the second voltage VSS, the shift register unit 100 has a relatively large power consumption and heat.
What is needed, therefore, is a shift register which can overcome the above-described deficiencies. What is also needed is an LCD device including the shift register.